As a semiconductor device is miniaturized, a characteristic variation of a transistor increases. In a SRAM, since a transistor smaller than a logic circuit is used, the characteristic variation is larger than that of the logic circuit. Especially when a power supply voltage is low, it is difficult to hold the write margin of the SRAM against the characteristic variation.
In order to secure the write margin of the SRAM, there is a method of making a low potential of a bit line become a negative potential at the time of writing. In order to effectively operate the method of making the bit line become a negative potential at the time of writing, the value of the negative potential of the bit line and a timing of switching the bit line to the negative potential are required to be controlled with high accuracy.
If the value of the negative potential of the bit line is significantly increased, a nonselected cell is erroneously written. If the bit line is switched to the negative potential at a significantly early timing, a sufficient negative potential cannot be applied to the bit line. Meanwhile, if the bit line is switched to the negative potential at a significantly late timing, it takes a longer time for writing operation.